Introduction to Logic Design Using Verilog HDL

This chapter provides an introduction to the design methodologies and modeling constructs of the Verilog hardware description language. It presents modules, ports and test benches. The chapter introduces Verilog in conjunction with combinational logic and sequential logic. It also presents dataflow modeling which is at a higher level of abstraction than built-in primitives or user-defined primitives. Dataflow modeling corresponds one-to-one with conventional logic design at the gate level. Logic elements are the constituent parts of the Verilog language. They consist of comments, logic gates, parameters, procedural control statements which modify the flow of control in a behavior, and data types. A multiplexer is a logic macro device that allows digital information from two or more data inputs to be directed to a single output. Data input selection is controlled by a set of select inputs that determine which data input is gated to the output.