Mechanical Dicing Challenges and Development on 50um Saw Street with Wafer Backside Coating (WBC)
Ying Heong Chiew, J. Y. Liong, F.F. Tan
Abstract
Ying Heong Chiew, J. Y. Liong, F.F. Tan
Abstract
The continuing package miniaturized on semiconductor industry had driven toward smaller feature sizes and higher density which will raise the hurdle of dicing. This has become a trend to increase the number of potential die per wafer (PDPW) by shrinking the saw street width to have a competitive product cost and strategically maintain the product margin that affected by yearly Average Selling Price (ASP) erosion. Producing a wafer is a fixed cost thus the more die per wafer equates to lower cost per die. Each die is separated from its neighbors by narrow saw street, which are the cut lines for singulating the die. The narrower saw street width, the more dies per wafer and the more challenging the dicing. Generally, the width of the saw streets has been reduced from former industry standard of 85um to 60um and now to latest 50um. The dicing challenges and quality issue become more crucial with the requirement of wafer backside coating (WBC), smaller die size, thinner wafer with passivation stacks on the saw street and existing of process control monitor (PCM) areas which contains the massive test structures. Key dicing quality characteristics focused in this paper are including top side chipping, passivation peeling and die side wall damage. This is most severe issue in dicing process and has induced the quality risk of customer return due to not easy or impossible to screen out at final test for those minor chipped/cracked die. Qualitative analysis will be carried out and high power microscope will be used to check for chipping condition or other defects. This paper reports the challenges faced and the successful development of 50um narrow saw street with conductive and nonconductive wafer backside coating on various thickness of wafers with six sigma process capability dicing performance and passed all the reliability stress test requirements. A comprehensive study was performed in optimizing critical dicing parameter such as blade height, suitable dicing blade and dicing tape.
OpenAlex reports 6 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
The continuing package miniaturized on semiconductor industry had driven toward smaller feature sizes and higher density which will raise the hurdle of dicing. This has become a trend to increase the number of potential die per wafer (PDPW) by shrinking the saw street width to have a competitive product cost and strategically maintain the product margin that affected by yearly Average Selling Price (ASP) erosion. Producing a wafer is a fixed cost thus the more die per wafer equates to lower cost per die. Each die is separated from its neighbors by narrow saw street, which are the cut lines for singulating the die. The narrower saw street width, the more dies per wafer and the more challenging the dicing. Generally, the width of the saw streets has been reduced from former industry standard of 85um to 60um and now to latest 50um. The dicing challenges and quality issue become more crucial with the requirement of wafer backside coating (WBC), smaller die size, thinner wafer with passivation stacks on the saw street and existing of process control monitor (PCM) areas which contains the massive test structures. Key dicing quality characteristics focused in this paper are including top side chipping, passivation peeling and die side wall damage. This is most severe issue in dicing process and has induced the quality risk of customer return due to not easy or impossible to screen out at final test for those minor chipped/cracked die. Qualitative analysis will be carried out and high power microscope will be used to check for chipping condition or other defects. This paper reports the challenges faced and the successful development of 50um narrow saw street with conductive and nonconductive wafer backside coating on various thickness of wafers with six sigma process capability dicing performance and passed all the reliability stress test requirements. A comprehensive study was performed in optimizing critical dicing parameter such as blade height, suitable dicing blade and dicing tape.
Key concepts: Wafer dicing, Wafer, Die (integrated circuit), Wafer testing, Passivation, Die preparation, Materials science, Coating