Novel algorithm for symmetric encryption

The paper presents a new algorithm for block cipher with symmetric encryption and decryption algorithm. The main features of this idea are the large size of the key and high processing speed. This algorithm is based on reversible logic. The physical implementation of reversible gates will be done in the future. These gates can be modeled using FPGA structures. Contemporary FPGA chips contains very large numbers of elements and this feature allows implementation of complex reversible circuits. These circuits consists of long gates cascades and in one chip it is possible to embed many of them. Usually the encryption algorithms are implemented as programs using a processor with proper software. The algorithm presented in this paper allows to build a cipher with one FPGA chip.