Accurate Inductance Modeling of 3-D Inductor Based on TSV

In this letter, an accurate model for the inductance of 3-D integrated inductor based on through silicon via is proposed. The model, considering both the internal inductance and detailed calculation of redistribution layer inductance, can more precisely obtain the total inductance of 3-D inductor using negligible computational time. Compared with the results of the Q3D extractor, the inductance results obtained from the proposed model exhibit good agreement with various design parameter ranges. The maximum error is less than 3.5%, so our model achieves high accuracy.