Monitor and control for the SKA1 CSP Mid.CBF utilizing the Stratix-10 FPGA equipped with HPS

We present design considerations and a prototyping progress report for a low-level monitor and control communication system designed to operate on the Stratix-10 System on a Chip (SoC) Field Programmable Gate Array (FPGA) equipped with a Hard Processor System (HPS). The goal of this activity is to allow remote clients to use high level communication protocols (ie. TANGO) to access IP blocks within a Stratix-10 FPGA chip by taking advantage of very low latency communication between HPS and the FPGA fabric, eliminating the need to implement Ethernet protocols within the FPGA logic.