A 10-bit high speed pipelined ADC

The design of a 10-bit, 200MS/s Pipelined Analog to Digital Converter (ADC) is presented in this paper. The implemented pipelined ADC employs techniques such as pipeline stage scaling algorithm, to lower power, capacitor ratio independent conversion scheme, a nested gain boosting technique and thin oxide transistors with clock bootstrapping. The fully realized is measured under different input frequencies with a sampling rate of 200MS/s and it consumes 46.8mW from a 1.8V power supply. The pipelined ADC implemented in 130nm CMOS technology exhibits signal-to-noise plus distortion ration SNDR of 54.7dB and occupies a die area of 0.31mm2.