Design and application of RISC processor

This paper presents the design of multi-cycle 32-bit Reduced Instruction Set Computer (RISC) processor for better performance and higher speed of operation. The processor is capable of executing more number of instructions with simple design and less critical path delay. The designed processor was simulated and synthesized using Xilinx 14.7 ISE design suite. The processor executes each and every instruction in more than one cycle that's why the term multi-cycle. Each instruction is divided into three main states namely the Fetch state, the Decode state and the Execution state. The first two sates remain the same for all the instruction the last state, however depends on the type of operation performed in that instruction.