A 0.19 ppm/°C bandgap reference circuit with high-PSRR
Jing Ping Leng, Yangyang Lu, Yunwu Zhang, Huan Xu, Kongsheng Hu, Zhicheng Yu, Weifeng Sun, Jing Zhu
Abstract
Jing Ping Leng, Yangyang Lu, Yunwu Zhang, Huan Xu, Kongsheng Hu, Zhicheng Yu, Weifeng Sun, Jing Zhu
Abstract
A high-order curvature-compensated CMOS bandgap reference (BGR) topology with a low temperature coefficient (TC) over a wide temperature range and a high power supply reject ratio (PSRR) is presented. High-order correction is realized by incorporating a nonlinear current I NL , which is generated by ∆ V GS across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μ m 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of 0.19 ppm/°C over the temperature range of 165 °C (−40 to 125 °C), PSRR of −123 dB @ DC and −56 dB @ 100 kHz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.
A significance statement is not available in the OpenAlex record.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
A high-order curvature-compensated CMOS bandgap reference (BGR) topology with a low temperature coefficient (TC) over a wide temperature range and a high power supply reject ratio (PSRR) is presented. High-order correction is realized by incorporating a nonlinear current I NL , which is generated by ∆ V GS across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μ m 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of 0.19 ppm/°C over the temperature range of 165 °C (−40 to 125 °C), PSRR of −123 dB @ DC and −56 dB @ 100 kHz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.
Key concepts: Power supply rejection ratio, Bandgap voltage reference, Materials science, Optoelectronics, Electrical engineering, Engineering, Voltage reference, CMOS