Fpga Based Convolution Encoder Time Domain And State Machine Design Using Vhdl

VHDL 1 1 1 sequence [g , g ,……, g ]{Here ,x represents the number 0 1 x of points from where bits are extracted for modulo-2-adders}denotes the impulse response for path p1 and the 2 2 2 sequence [g , g ,……, g ]denotes the impulse response 2 2 x of path p2.There two impulse responses are obtained by determining the two output sequences of the encoder that are produced in response to the input sequence (1,0,0,…..).The impulse response so defined is called the generator sequence of the code.