Design And Implementation Of Cache Memory With Fifo Cache-Control

In this era, use of laptops, computers, mobiles etc has became an inherent part of human life. The speed of the processor is the main requirement in all these devices. The parallelism and the use of multi-core processor increases the speed of calculation. From the shared resources, consistency in data stored is referred by cache coherence (Kolhe et al., 2014) . The cache controller controls the cache coherence. Many of the computers are designed to use memory in an organized way. The speed of the processors depend upon various factors such as Random Access Memory (RAM), Memories etc. Cache memory is the temporary memory location. which stores the supporting files of the running files. This supports easy access of files, running in the background or closed recently. In computing application, Field-Programmable Gate Array (FPGA) plays a major role. The FPGA hardware in computing applications improves the energy-efficiency By magnitude and throughput of the running processor (Hanumaiah and Vrudhula, 2014) . From the variety of memory architectures, the better one is where the data shared between the processor and accelerators resides in a memory, between the cache memory and main memory. Due to this architecture, the model becomes simple and also the cache coherency is avoided. Since the cache memory is a temporary memory, it reduces the computation time. The operation of on operand becomes faster as compared to the main memory. This cache memory is a small block of memory used for easy access. The induced miss-rate in the cache memory is tracked by cache controller (Wang and Tian, n.d.). When the processor wants to access any data, initially it is searched in the cache memory and if the data is not present, then the accessing of main memory is done. The process of searching data in the cache memory is known as 'cache hit'. Since, cache memory stores the corresponding data