Differential double tail dynamic CMOS voltage comparator
Priyesh P. Gandhi, Niranjan M. Devashrayee
Abstract
Priyesh P. Gandhi, Niranjan M. Devashrayee
Abstract
This paper presents a new differential double tail high-performance dynamic comparator suitable for low-voltage low-power applications. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in 180nm technology with ±0.9V supply. The proposed comparator has very wide dynamic range, low offset, low propagation delay with less power dissipation as compared to other architectures.
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This paper presents a new differential double tail high-performance dynamic comparator suitable for low-voltage low-power applications. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in 180nm technology with ±0.9V supply. The proposed comparator has very wide dynamic range, low offset, low propagation delay with less power dissipation as compared to other architectures.
Key concepts: Comparator, Input offset voltage, Comparator applications, CMOS, Offset (computer science), Computer science, Electronic engineering, Voltage