Testing Clock Distribution Networks

Signals in a digital system are coordinated by one or multiple clocks. To ensure the correct system operations, ideally all clock signals derived from a clock source should be synchronized through a clock distribution network (CDN). Clock delay faults in a CDN may create clock skews, which will change the timing behavior of a circuit and produce invalid results. Unfortunately, it is very difficult to detect such faults directly due to the large number of clock sinks and the lack of observability on the clock signals, and this topic is rarely studied previously. In this paper, we present a systematic way to detect faulty timing behavior due to the clock delay in a CDN. For each clock skew under test, we need to find out the longest sensitizable path in the combinational logic that can be used to detect the corresponding clock skew. Such structural paths can be found through static timing analysis (STA) or statistical STA. Launch-on-capture (LOC) test patterns for the candidate paths are then generated and compacted. Experimental results show that most of clock skews can be detected with a limited number of test vectors.