2017Unpublished venueRequires access

Energy-efficient standby current suppression with bootstrapped power-gating technique

Yingchieh Ho, Chen Hsu

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Abstract

This paper presents a bootstrapped power-gating technique for suppressing standby current using a modified dynamic standby control (DSC). The modified DSC recharges the gate voltage by a keeper, which maintains the power gates cut-off with negative overdrive voltage. In order to achieve high energy-efficiency, a current sensor is used to observe total standby current on power gates and DSC. Based on the current sensor, the minimal standby current can be found even in different PVT corners. The bootstrapped power-gating technique is simulated in 65nm CMOS process. According to simulation results, energy-efficient standby current can be found by adjusting the recharging rate of DSC.

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What this paper is about

This paper presents a bootstrapped power-gating technique for suppressing standby current using a modified dynamic standby control (DSC). The modified DSC recharges the gate voltage by a keeper, which maintains the power gates cut-off with negative overdrive voltage. In order to achieve high energy-efficiency, a current sensor is used to observe total standby current on power gates and DSC. Based on the current sensor, the minimal standby current can be found even in different PVT corners. The bootstrapped power-gating technique is simulated in 65nm CMOS process. According to simulation results, energy-efficient standby current can be found by adjusting the recharging rate of DSC.

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Available abstract

This paper presents a bootstrapped power-gating technique for suppressing standby current using a modified dynamic standby control (DSC). The modified DSC recharges the gate voltage by a keeper, which maintains the power gates cut-off with negative overdrive voltage. In order to achieve high energy-efficiency, a current sensor is used to observe total standby current on power gates and DSC. Based on the current sensor, the minimal standby current can be found even in different PVT corners. The bootstrapped power-gating technique is simulated in 65nm CMOS process. According to simulation results, energy-efficient standby current can be found by adjusting the recharging rate of DSC.

Key concepts: Standby power, Power gating, Voltage, CMOS, Current (fluid), Logic gate, Power (physics), Electrical engineering

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