2017•Unpublished venueRequires access
A 14-bit 5 MS/s split non-binary SAR ADC
Shu Ren Yang, Minghang Liu, Yusong Mu, Yuchun Chang
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Abstract
This paper presents a high resolution successive approximation register (SAR) analog-to-digital converter (ADC). The prototype is designed with a 1P4M 0.18 μm CMOS technology. At 1.8V supply the SAR ADC consumes 1.19mW. It achieves an ENOB of 13.65bit, an SNDR of 84dB, and an SFDR of 88.2dB at Nyquist input frequency. The ADC core occupies an active area of 500μm × 500μm.