A scalable VHDL-implementation technique of the binary encoder structure into FPGA

The problem of scalable and optimal behavior-style description of the binary encoder implementation into FPGA was examined. The structural synthesis technique of the binary encoder with input requests filtration and error detection circuits, which allow improving FPGA resource utilization in comparison with typical description, was proposed. The results of research and development, which have presented by relationship equations for encoder and its structure generation algorithm, were confirmed by correct register-transfer level representation and during timing simulation. The numeric comparative assessments of FPGA recourses utilizing depending both the encoder inputs number and FPGA ICs family from different vendor was implemented.