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2017•Unpublished venueRequires access

Deterministic methodology to evaluate BTI impact on logic gates propagation delay

Gabriela Firpo Furtado, Thiago H. Both, Gilson Wirth

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Abstract

The propagation delay variation induced by BTI in logic gates is studied. Using the deterministic BTI model introduced by our group in [1], a detailed description of its implementation in a commercial SPICE tool is presented. Simulations concerning the dependence of the BTI-induced propagation delay on the supply voltage and on the DC stress time of NAND gates are presented. The different impact of BTI for both low-high-low and high-low-high levels pulses is evaluated.

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What this paper is about

The propagation delay variation induced by BTI in logic gates is studied. Using the deterministic BTI model introduced by our group in [1], a detailed description of its implementation in a commercial SPICE tool is presented. Simulations concerning the dependence of the BTI-induced propagation delay on the supply voltage and on the DC stress time of NAND gates are presented. The different impact of BTI for both low-high-low and high-low-high levels pulses is evaluated.

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Available abstract

The propagation delay variation induced by BTI in logic gates is studied. Using the deterministic BTI model introduced by our group in [1], a detailed description of its implementation in a commercial SPICE tool is presented. Simulations concerning the dependence of the BTI-induced propagation delay on the supply voltage and on the DC stress time of NAND gates are presented. The different impact of BTI for both low-high-low and high-low-high levels pulses is evaluated.

Key concepts: NAND gate, Propagation delay, Spice, Logic gate, Electronic engineering, Delay calculation, NMOS logic, NAND logic

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