Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units

Recent processor architectures expose their datapaths to the compiler so that the compiler not only takes care of scheduling instructions to the available processing units but also of scheduling the data transports between the processing units. Bypassing register usage this way generally allows the compiler to improve the degree of instruction-level parallelism. However, the current compiler technology is still based on code generation done by a depth-first traversal on the syntax trees that makes use of as few registers as possible. Code generators inspired from queue machines can better utilize the register bypassing capability of exposed datapath architectures with buffered processing units. In this paper, we encode the decision version of optimal code generation as a satisfiability modulo theories (SMT) problem and use SMT solvers to generate optimal code that maximizes the instruction-level parallelism (ILP) for a given number of processing units. Our experimental results clearly demonstrate the potential of exposed datapath architectures to utilize ILP contained in basic blocks to the fullest by relying on our recently suggested queue-based code generation. Second, it is also shown that the queue-based code generation technique produces more efficient code than classic compiler techniques.