Event-driven simulation of digital circuits using modified Petri nets algorithm

This paper presents a modified Petri nets simulation algorithm applied as an engine for a logic simulator in digital integrated circuit design. The simulator uses an event-driven algorithm and eliminates the delta delay which occurs in the majority of modern simulation algorithms. The algorithm has been tested for the logic simulation of combinational digital circuits and demonstrated more accurate simulation results. This has been achieved due to solving the issue of the priority choice problem when two or more events are occurring simultaneously.