An SIC-BS linear feedback shift register for low power BIST

In the existing high speed, highly advanced technology of IC designs, the need of efficient pattern generator to minimize the test power dissipation without affecting the overall system performance. Built in Self Test (BIST) is promising DFT technique and the extremely important module. The most widely implemented pattern generator used in BIST is Linear Feedback Shift Register (LFSR) because of its small area overhead and excellent pseudo random characteristics. The proposed single input change BS LFSR which are Ex-OR with non zero selective seed, generated by the BS-LFSR. The generated test vectors are significantly enhance the correlation between the test sequences. We have tested and compared with conventional techniques and results are very effective. This approach decreases the transition activity, dynamic power dissipation and increases the fault coverage.