Sequential adiabatic logic for ultra low power applications

The principal objective of this work is to provide new low power solutions for VLSI design engineers. This work focuses on the reduction of power dissipation by taking advantage of adiabatic logic. The switching power requirement of conventional CMOS circuits has become a major concern in VLSI systems. In this paper new ultra low power logic called adiabatic logic or energy recovery logic is presented. We have design various DFF cells using various energy recovery logic. Power consumption is calculated by VLSI EDA Tools and compared with conventional CMOS DFF.