2017Unpublished venueRequires access

A 12-bit 200KS/s SAR ADC with digital self-calibration

Xiaojie Zhang, Maodong Wang, Liyang Guo, Xinghua Wang

Open publisher page 3 citations

Abstract

Aiming at the application of neural signal detection system, this paper designs a 12-bit 200KS/s high resolution successive approximation analog-to-digital converter (SAR ADC) fabricated in SMIC 0.18-μm process. An optimized digital self-calibration technique is proposed to correct the static offset of the comparator and the mismatch of the capacitor array by using a correction capacitor array, achieving 1-bit improvement of ENOB. Simulation results show that, when the input signal is 46K, the ADC fulfills an SNDR of 71.55dB and an SFDR of 91.82dB with a 200KS/s sampling rate, while the ADC only can achieve an SNDR of 65.85dB and an SFDR of 78.83dB before calibration. With the ENOB of 11.59 bit, the self-calibration SAR ADC consumes 336μW at 1.8 V power supply.

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What this paper is about

Aiming at the application of neural signal detection system, this paper designs a 12-bit 200KS/s high resolution successive approximation analog-to-digital converter (SAR ADC) fabricated in SMIC 0.18-μm process. An optimized digital self-calibration technique is proposed to correct the static offset of the comparator and the mismatch of the capacitor array by using a correction capacitor array, achieving 1-bit improvement of ENOB. Simulation results show that, when the input signal is 46K, the ADC fulfills an SNDR of 71.55dB and an SFDR of 91.82dB with a 200KS/s sampling rate, while the ADC only can achieve an SNDR of 65.85dB and an SFDR of 78.83dB before calibration. With the ENOB of 11.59 bit, the self-calibration SAR ADC consumes 336μW at 1.8 V power supply.

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Available abstract

Aiming at the application of neural signal detection system, this paper designs a 12-bit 200KS/s high resolution successive approximation analog-to-digital converter (SAR ADC) fabricated in SMIC 0.18-μm process. An optimized digital self-calibration technique is proposed to correct the static offset of the comparator and the mismatch of the capacitor array by using a correction capacitor array, achieving 1-bit improvement of ENOB. Simulation results show that, when the input signal is 46K, the ADC fulfills an SNDR of 71.55dB and an SFDR of 91.82dB with a 200KS/s sampling rate, while the ADC only can achieve an SNDR of 65.85dB and an SFDR of 78.83dB before calibration. With the ENOB of 11.59 bit, the self-calibration SAR ADC consumes 336μW at 1.8 V power supply.

Key concepts: Effective number of bits, Spurious-free dynamic range, Successive approximation ADC, Comparator, Capacitor, Electronic engineering, Calibration, 12-bit

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