Q PSK System Implementation on FPGA

SDR, a Software Defined Radio, was first proposed by Joseph Mitola in 1991. It is an important element of wireless technology and is a hot topic in the current telecommunication industry. SDR is defined as radio in which some or all of the physical layer functions are software defined. The main goal of SDR is to replace as many as possible analog and/or digital components with programmable devices. The radio typically has to load different waveform depending on their requirements, which may use different source coding, channel coding and modulation schemes. The objective of this paper is to demonstrate simulation and implementation of the QPSK modem on FPGA. FPGA is chosen as implementation platform due to its suitability for the real time algorithm implementation. FPGA has both high speed processing capability and good reconfigurable performance hence FPGA architecture is a viable solution for SDR technology. The QPSK modulator and demodulator algorithms are simulated using MATLAB R2013a and implemented on vertex 5(xc5vlx110t 1136-2) using Xilinx ISE 14.2 System Generator, Plan Ahead. The output waveforms are displayed and analyzed using Xilinx Chip Scope Pro.