2017•AEU - International Journal of Electronics and CommunicationsRequires access

A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information

Hamed Nasiri, Abdolreza Nabavi

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Key concepts: Comparator, Effective number of bits, Spurious-free dynamic range, Successive approximation ADC, 12-bit, Flash ADC, CMOS, Electronic engineering

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A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information — Research Paper | ScholarLens