2017•Unpublished venueRequires access

High resolution CMOS voltage comparator for high speed SAR ADCs

Nader Sharifi Gharabaghlo, Tohid Moradi Khaneshan

Open publisher page 7 citations

Abstract

By means of a standard 0.18μm CMOS process a novel CMOS voltage comparator circuit has been proposed which is capable of resolving 400μV. Employing preamplifier latch structure the designed circuit operates at the clock frequency of 100MHz. The main advantage of the implemented comparator is its 11 bit resolution which makes it a good choice for high resolution SAR ADCs. In order to reduce the power consumption some modifications are made to the conventional structure of the comparator which resulted in reduction of employed transistors as well as active area on chip. Post-layout simulation results confirm the correct behavior of the proposed architecture while the power dissipation is 900μW from a 1.8V power supply.

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What this paper is about

By means of a standard 0.18μm CMOS process a novel CMOS voltage comparator circuit has been proposed which is capable of resolving 400μV. Employing preamplifier latch structure the designed circuit operates at the clock frequency of 100MHz. The main advantage of the implemented comparator is its 11 bit resolution which makes it a good choice for high resolution SAR ADCs. In order to reduce the power consumption some modifications are made to the conventional structure of the comparator which resulted in reduction of employed transistors as well as active area on chip. Post-layout simulation results confirm the correct behavior of the proposed architecture while the power dissipation is 900μW from a 1.8V power supply.

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OpenAlex reports 7 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

By means of a standard 0.18μm CMOS process a novel CMOS voltage comparator circuit has been proposed which is capable of resolving 400μV. Employing preamplifier latch structure the designed circuit operates at the clock frequency of 100MHz. The main advantage of the implemented comparator is its 11 bit resolution which makes it a good choice for high resolution SAR ADCs. In order to reduce the power consumption some modifications are made to the conventional structure of the comparator which resulted in reduction of employed transistors as well as active area on chip. Post-layout simulation results confirm the correct behavior of the proposed architecture while the power dissipation is 900μW from a 1.8V power supply.

Key concepts: Comparator, CMOS, Preamplifier, Electronic engineering, Comparator applications, Transistor, Computer science, Dissipation

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