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A novel ultra-low-power time-domain comparator based on subthreshold source-coupled logic

Samaneh Babayan-Mashhadi, Sajjad Mortazavi

Open publisher page 4 citations

Abstract

This paper presents a novel approach for designing ultra-low power, low-voltage time-domain comparators using source-coupled logic (SCL) topology, operating in weak-inversion (subthreshold) regime (STSCL). The proposed time-domain comparator (TDC) is simulated in 0.18μm CMOS technology. Simulation results reveal that at low supply voltage of 0.5V, the comparator consumes only 0.8μW operating at 1.1MHz, with the accuracy of approximately 1mV.

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What this paper is about

This paper presents a novel approach for designing ultra-low power, low-voltage time-domain comparators using source-coupled logic (SCL) topology, operating in weak-inversion (subthreshold) regime (STSCL). The proposed time-domain comparator (TDC) is simulated in 0.18μm CMOS technology. Simulation results reveal that at low supply voltage of 0.5V, the comparator consumes only 0.8μW operating at 1.1MHz, with the accuracy of approximately 1mV.

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OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper presents a novel approach for designing ultra-low power, low-voltage time-domain comparators using source-coupled logic (SCL) topology, operating in weak-inversion (subthreshold) regime (STSCL). The proposed time-domain comparator (TDC) is simulated in 0.18μm CMOS technology. Simulation results reveal that at low supply voltage of 0.5V, the comparator consumes only 0.8μW operating at 1.1MHz, with the accuracy of approximately 1mV.

Key concepts: Comparator, Subthreshold conduction, CMOS, Electronic engineering, Logic gate, Voltage, Computer science, Electrical engineering

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