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2017•Unpublished venueRequires access

Silicon tunnel FET with average subthreshold slope of 55mV/dec at low drain currents

K. Narimani, S. Glass, Torsten Rieger, P. Bernardy, Nils von den Driesch, S. Mantl, Qing‐Tai Zhao

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Abstract

In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves Ion/Ioffratio of 5×104considering Ion(Von= VIoff-0.5V) = 0.8×10-8μA/μm and an average SS of 55mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Idbeats the MOSFET performance at lower currents.

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What this paper is about

In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves Ion/Ioffratio of 5×104considering Ion(Von= VIoff-0.5V) = 0.8×10-8μA/μm and an average SS of 55mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Idbeats the MOSFET performance at lower currents.

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Available abstract

In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves Ion/Ioffratio of 5×104considering Ion(Von= VIoff-0.5V) = 0.8×10-8μA/μm and an average SS of 55mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Idbeats the MOSFET performance at lower currents.

Key concepts: Computer science, Algorithm, Physics

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