Linking high-level synthesis with physical design

With advance in semiconductor technology and increases in design complexity, High Level Synthesis (HLS) is becoming the methodology of choice for shortening the design time by allowing the user to start from a behavioral specification. However, the prevalent Application-Specific Integrated Circuit (ASIC) design methodology separates HLS from physical design, which includes placement and routing, extraction, back-annotation and physical verification. The methodology becomes less feasible as the significance of interconnect delay can no longer be ignored even in the early stages of HLS. To develop a feasible approach for HLS that models reality, layout driven synthesis by incorporating layout information into HLS tasks is proposed. It allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This feature is highly desirable in order to avoid unnecessary iterations through the design process. This dissertation first presents a layout driven synthesis process. After that, it presents various techniques needed for layout driven synthesis. The techniques include component and chip level estimation for Field Programmable Gate Array (FPGA) and layout driven scheduling-binding. Experiments were performed to demonstrate the feasibility of the methodology and techniques, and the efficiency of the algorithms. Finally, the results are presented in this dissertation.