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2010•CiiT international journal of programmable device circuits and systemsRequires access

A Survey on Single and Double Edge-Triggered Flip-Flops to Design Scan Flip-Flop Cell

D. Satya Valibaba, S. Sivanantham

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Abstract

This paper elucidates about different topologies of both SET&DET flip-flops and investigated under estimation of performance metrics like Power consumption, delay (D-Q), Area, Transistor Count, Number of Clocked Transistors, PDP and EDP extensively. Based on this survey a new low power, less area occupied, high performance Pulsed scan flip-flop cell is proposed.

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What this paper is about

This paper elucidates about different topologies of both SET&DET flip-flops and investigated under estimation of performance metrics like Power consumption, delay (D-Q), Area, Transistor Count, Number of Clocked Transistors, PDP and EDP extensively. Based on this survey a new low power, less area occupied, high performance Pulsed scan flip-flop cell is proposed.

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Available abstract

This paper elucidates about different topologies of both SET&DET flip-flops and investigated under estimation of performance metrics like Power consumption, delay (D-Q), Area, Transistor Count, Number of Clocked Transistors, PDP and EDP extensively. Based on this survey a new low power, less area occupied, high performance Pulsed scan flip-flop cell is proposed.

Key concepts: Flip-flop, Flip, FLOPS, Transistor count, Transistor, Power consumption, Electronic engineering, Power (physics)

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