WATCHDOG TIMER USING VHDL FOR ATM SYSTEM

A watchdog timer is a computer hardware timing device that triggers a system reset if the main program, due to some fault condition, such as a hang, neglects to regularly service the watchdog. The intention is to bring the system back from the hung state into normal operation. Such a timer has got various important applications, one of them being in ATMs which we have studied in our paper. We can implement watchdog timer by using hardware as well as software. The advantage of implement it using software rather than hardware is that it will required less power consumption, less cost and we obtain high speed compare to hardware. The compatible or good known language for Xilinx is VHDL. The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires) and information theory. The simulation tool that we have used is Xilinx 6.2i . Xilinx provide platform for VHDL. First the required code for timer circuit was written in VHDL and simulated so as to obtain the required output waveforms. After the coding was completed, VHDL model is translated into the gates and wires that are mapped onto a programmable logic device. The programmable logic device used here is Spartan-II. The above coding and burning methods were completed and the output was observed on FPGA kit. The timer code was implemented using VHDL while burning was done using Spartan-II kit.