2017Unpublished venueRequires access

A 30.5 GHz fully integrated frequency synthesizer in SiGe BiCMOS for 61 GHz and 122 GHz radar applications

Maciej Kucharski, Arzu Ergintav, Frank Herzel, Dietmar Kissinger, Herman Jalli Ng

Open publisher page 2 citations

Abstract

This paper presents a fully integrated millimeter-wave phase-locked loop (PLL) frequency synthesizer fabricated in 130nm BiCMOS technology. It comprises a self-buffered voltage controlled oscillator (VCO) tunable from 29.4 to 33.0 GHz, which corresponds to 11.5% tuning range. The VCO contains a programmable binary weighted varactor bank for phase noise reduction due to configurable low VCO gain. A programmable 4-bit charge pump (CP) was designed in order to compensate for VCO gain variation. It provides fast switching and shows low mismatch between UP and DN currents. The measured phase noise of the PLL is -85 dBc/Hz and -100 dBc/Hz at 150 kHz and 1MHz offset from the carrier, respectively. The circuit draws 60mA from 3.3 V supply. It is demonstrated that the presented chip can be successfully used in FMCW radar applications.

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What this paper is about

This paper presents a fully integrated millimeter-wave phase-locked loop (PLL) frequency synthesizer fabricated in 130nm BiCMOS technology. It comprises a self-buffered voltage controlled oscillator (VCO) tunable from 29.4 to 33.0 GHz, which corresponds to 11.5% tuning range. The VCO contains a programmable binary weighted varactor bank for phase noise reduction due to configurable low VCO gain. A programmable 4-bit charge pump (CP) was designed in order to compensate for VCO gain variation. It provides fast switching and shows low mismatch between UP and DN currents. The measured phase noise of the PLL is -85 dBc/Hz and -100 dBc/Hz at 150 kHz and 1MHz offset from the carrier, respectively. The circuit draws 60mA from 3.3 V supply. It is demonstrated that the presented chip can be successfully used in FMCW radar applications.

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Available abstract

This paper presents a fully integrated millimeter-wave phase-locked loop (PLL) frequency synthesizer fabricated in 130nm BiCMOS technology. It comprises a self-buffered voltage controlled oscillator (VCO) tunable from 29.4 to 33.0 GHz, which corresponds to 11.5% tuning range. The VCO contains a programmable binary weighted varactor bank for phase noise reduction due to configurable low VCO gain. A programmable 4-bit charge pump (CP) was designed in order to compensate for VCO gain variation. It provides fast switching and shows low mismatch between UP and DN currents. The measured phase noise of the PLL is -85 dBc/Hz and -100 dBc/Hz at 150 kHz and 1MHz offset from the carrier, respectively. The circuit draws 60mA from 3.3 V supply. It is demonstrated that the presented chip can be successfully used in FMCW radar applications.

Key concepts: Voltage-controlled oscillator, Phase noise, Phase-locked loop, dBc, Varicap, Frequency synthesizer, BiCMOS, Electrical engineering

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