Vedic and conventional methods of N × N Binary Multiplication with hardware implementation

A comparative study of the resources involved in the Multiplication of two N-Bit binary numbers is performed using a Vedic Multiplication and the Modern Binary Multiplication techniques. A generic Vedic method for N × N Binary Multiplication is presented. From first principles, using logic gates, an N × N Binary Multiplication is performed using both the methods for different number of bits, using Transistor Transistor Logic (TTL) gates. It is found that the propagation delay encountered while using the Vedic Multiplication technique is lesser, more so when the size of multiplication is more. Additionally, Nikhilam Sutra is presented for Multiplication of large binary numbers close to a chosen base and comments are made as to how such Multiplication are effectively reduced to Multiplication of smaller numbers.