An innovative Booth algorithm

Large-width multiplier is one of the most important computing units, such as for encrypt chip basing on RSA algorithm. In this paper, a circuit structure which is the optimized multiplier with innovative Booth algorithm is put forward. We proposed an innovative algorithm that can be generalized to N-bit multiplier design. Meanwhile, comparing to the original Booth multiplier, it speeds up the computation from the time complexity. Furthermore, its parallel computation characteristic makes it more suitable for large number multiplier. We implement our algorithm in a FPGA board, which shows a much better performance comparing with the multiplier of original Booth and the one from Xilinx: the logic delay gets reduced by 9.3%. In addition, we also proposed method of design that multiplier is easy to extend to the N-bit.