2014•IEICE Technical Report; IEICE Tech. Rep.Requires access

Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator

Okamoto Takashi, Kuga Morihiro, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

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Key concepts: Application-specific integrated circuit, Field-programmable gate array, Computer science, Embedded system, Mechanism (biology), Serial communication, FPGA prototype, Computer hardware

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Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator — Research Paper | ScholarLens