A rail-to-rail noise-shaping non-binary SAR ADC

This paper presents a 10-bit, 5.12 kS/s noise-shaping non-binary successive approximation ADC (SAR ADC). The proposed noise-shaping SAR ADC requires an additional capacitor and a buffer along with a non-binary SAR ADC to implement the first order noise-shaping of the quantization error. The structure operates with a rail-to-rail input and yields a very high dynamic range of about 89.3dB. This is a novel approach to garner the advantages of noise-shaping along with the higher effective number of bits (ENOB) offered by a non-binary SAR ADC. The design also implements a 2-stage cascaded integrator comb decimation filter. The ADC implemented in a 0.18μm CMOS process occupies an active area of 0.31mm2. It achieves a good differential non-linearity of less than ±0.48LSB and integral non-linearity of less than ±0.9LSB. With a -0.5dBFS input signal the ADC obtains an SNDR of 88dB in 40Hz bandwidth after decimation. This corresponds to an ENOB of 14.3. The ADC requires about 20μW power from a 1.8V supply leading to a Figure of Merit (FoM) of 151dB.