K. Pakalniškis, E. Kazanavičius
Abstract
The paper shows the concepts of high level synthesis with SystemC. One important aspect of using SystemC classes is that you can use the same environment for all steps in the synthesis flow. This concept makes the unified system design methodology starting from functional verification to synthesis and architectural verification.
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The paper shows the concepts of high level synthesis with SystemC. One important aspect of using SystemC classes is that you can use the same environment for all steps in the synthesis flow. This concept makes the unified system design methodology starting from functional verification to synthesis and architectural verification.
Key concepts: SystemC, High-level synthesis, Computer science, Electronic system-level design and verification, Design flow, Computer architecture, Programming language, Embedded system