Compiler optimization for superscalar and pipelined processors

The exploitation of parallelism at both the multiprocessor or multicore level and at the instruction level is the means to achieve high-performance. The compiler for VLIW and superscalar processors must expose sufficient parallelism to effectively utilize the parallel hardware. The amount of instruction level parallelism available to VLIW processors or superscalar processors can be limited. This will limit the performance of these processors to a certain extent. However, with compiler optimization techniques, its performance can be increased to greater extent. This evaluation shows that utilizing the existing resources of the processor with certain programmer constraints and an efficient scheduling of independent and dependent blocks of instructions, we can increase the performance of the processors. As compiler optimization interact with the micro-architecture in complex ways, certain programmer constraints can be added to reduce the complexity and help the compiler to structure the Assembly code in a manner which can be used for out-of-order execution of the code. This paper provides new methods and improvements for the structure of the Assembly code for execution on superscalar processors.