Efficient Hardware Architecture for Compressed Sensing with DFT Sensing Matrix

The reconstruction of a sparse signal from an undersampled set of linear measurements can be found in many engineering fields. In some practical applications, the measurements are usually acquired through low-resolution analog-to-digital converters because of the limitations in hardware complexity and power consumption. In this paper, we present the first hardware architectural design for an optimal signal recovery from coarsely quantized measurements, in which the sensing matrix is a partial discrete Fourier transform matrix. The optimal signal recovery can be achieved using a novel turbo-type algorithm. We develop a variety of approximations at the algorithm level and employ pipelining and folding techniques, which enable high-efficiency and low-complexity implementation.