Microarchitectures for high performance, power efficient network processors

This dissertation introduces several optimizations to increase the performance of Network Processors and to reduce their power consumption. Changes in the computer network technologies motivates the employment of Network Processors, which are flexible, yet powerful processors optimized for networking applications. This thesis contributes to this field in the following ways. First, a benchmark for Network Processors is introduced, which can be used to evaluate different network processors architectures. In addition, this benchmark is used to show that the workloads of networking applications are statistically different from other domains such as the applications for media processors. Then, a flexible accelerator is introduced that can implement several key tasks in such applications. With the changes in processor manufacturing technologies, global structures in processors are becoming an important bottleneck. Since this accelerator can implement a variety of tasks, it can be used in all processing cores, eliminating an important shared resource in Network Processors. Third, this thesis introduces several power reduction techniques: victim caches for reducing the accesses to global structures and high level caches, cache miss detection, data filtering engine. Finally, a combined hardware/software approach is introduced that divides networking tasks into small independent code segments allowing each segment to be executed in parallel.