High performance and low power ONOFIC approach for VLSI CMOS circuits design

Improving high performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been implemented. The proposed method reduces the power dissipation and improves the speed of a VLSI circuit design. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they are not suitable for actual requirements. The proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and increased performance in VLSI circuits. Thus, the proposed ONOFIC approach results have been compared with LECTOR technique and observed that the proposed technique shows the improved performance and reduced power dissipation. The tool used for implementing the design is Tanner EDA.