Design of charge pump PLL using improved performance ring VCO

In this paper a PLL is designed at 0.18 μm CMOS technology and 3 V supply voltage. For performing phase and frequency synchronization the charge pump PLL utilizes four basic blocks which are phase detector, VCO, charge pump and first order low pass filter. An improved performance differential pair configuration based ring VCO has very high oscillation frequency up to 6.567 GHz at 2.5 V control voltage and power consumption of 6.8 mW. The phase frequency detector (PFD) is another part of PLL which is designed using CMOS realization of D-Flip Flop and NOR gate. The designed PLL has a power consumption of approximately 36 mW at the operating frequency of 500 MHz.