DESIGN OF POWER EFFICIENT 4x4 ARRAY MULTIPLIER USING ADIABATIC LOGIC

The main process of this paper is to reduce the power in array multiplier using adiabatic logic. Adiabatic logic is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic logic is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. With the help of TSPICE simulations, the power consumption is analyzed by variation of parameter. In existing method, two logic families, 2N-2P logic and 2N-2N2P logic are compared with conventional CMOS logic for array multiplier circuits. In proposed method, 2N-2P logic is enhanced by adding pull down network and power clock to reduce the power consumption. It is find that adiabatic technique is good choice for low power application in specified frequency range.