Optimized Modulo Multiplier Based On R.N.S

To implement long and repetitive multiplications of cryptographic and signal processing algorithm we often adopt residue number system. In this paper a new low power and low modulo multiplier foe well established {2 n -1,2 n ,2 n +1} based is proposed .Radix-8 Booth encoding technique is used in the proposed modulo 2 n -1 and modulo 2 n +1 multipliers. In the proposed modulo 2 n -1 multiplier, the number of partial products is lowered to (n/3)+1. For modulo 2 n +1 multiplication ,the aggregate bias due to the hard multiple and the modulo reduced partial product generation is composed of multiplier dependent dynamic bias and multiplier-independent static bias .In the proposed modulo 2 n +1 multiplier , the number of partial products is lowered to n/3+6 .For different modulo 2 n -1 and modulo 2 n +1 multiplier our proposed modulo multiplier consumes less area and has minimum power dissipation over radix-4 Booth encoded and non-encoded modulo multiplier.