RTL DESIGN AND VERIFICATION OF SPI MASTER-SLAVE USING UVM

The main objective of this paper is to design the SPI master-slave and verify the design using UVM. SPI stands for Serial Peripheral Interface. As the name suggests, SPI is a serial synchronous interface. It provides connection between the hosts usually, a microcontroller and slave devices. SPI interface is an On-chip interface. SPI protocol is one of the widely used serial protocols used in a SoC. The reason for its wide usage is its simplicity to use and have few signals to control. The SPI is designed in Verilog using Xilinx and the verification is done in UVM using QuestaSim.