FPGA Implementation of an Area Efficient Adaptive Edge based Bilinear Image Interpolation

Image interpolation is a significant task in various image processing applications. Bilinear image interpolation is one of the widely used techniques in many practical real time digital image scaling. The proposed algorithm is based on an efficient edge catching methodology. The proposed image scaling processor consists of a linear space-variant edge detector, combined filter and a simplified bilinear interpolation. The edge catching technique is used to improve the quality of image interpolation algorithm. The combined filter which acts as pre-filter to reduce the blurring effects produced by bilinear interpolation. This work proposes I model convolution kernel for combined filter to minimize the memory buffer consumption and the computing resources instead of using T-model and inversed T-model convolution kernels. The field programmable gate array (FPGA) implementation of this algorithm uses only 580 look up tables (LUTs) and it achieves highest peak signal to noise ratio (PSNR) as 37.02 by using combined filter with edge detector.