Design of optimized arithmetic circuits for multiplier realization

Arithmetic and Logic Unit (ALU) is a critical element in a CPU and multiplier is one of the important element in the ALU. In multipliers, for reducing partial products and computing result, multi-operand adders and fast adders are required. Fast adders can be constructed by parallel prefix networks but need new design methodologies for multi-operand adders. A special structure known as counters/compressors can be used for addition of multi-operands. In this paper a new counter architectures is presented for efficient multiplier design. Moreover, a fast sparse adder is proposed that can be used for final addition in the multiplier.