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A charge pump circuit using multi-staged voltage doubler clock scheme

Wen Chang Huang, Jin Chang Cheng, Po Chih Liou, Che Wei Liou

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Abstract

A high efficiency new charge pump circuit was proposed in the paper. A clock scheme which designed by multi-staged voltage doubler was used in the Dickson charge pump structure. Very high voltage could be reached through the pumping of the new charge pump circuit. By the simulation of HSpice under 0.35 μm process, 2V supply voltage and clock voltage. It showed a voltage up to 40.37V was obtained after seven-stage's pumping of the new circuit.

About this research paper

What this paper is about

A high efficiency new charge pump circuit was proposed in the paper. A clock scheme which designed by multi-staged voltage doubler was used in the Dickson charge pump structure. Very high voltage could be reached through the pumping of the new charge pump circuit. By the simulation of HSpice under 0.35 μm process, 2V supply voltage and clock voltage. It showed a voltage up to 40.37V was obtained after seven-stage's pumping of the new circuit.

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OpenAlex reports 6 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A high efficiency new charge pump circuit was proposed in the paper. A clock scheme which designed by multi-staged voltage doubler was used in the Dickson charge pump structure. Very high voltage could be reached through the pumping of the new charge pump circuit. By the simulation of HSpice under 0.35 μm process, 2V supply voltage and clock voltage. It showed a voltage up to 40.37V was obtained after seven-stage's pumping of the new circuit.

Key concepts: Voltage doubler, Charge pump, Voltage, Electrical engineering, Voltage multiplier, Voltage divider, CPU core voltage, Electronic engineering

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