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A Way of Enhancing Test Quality and Restraining the Increase of Test Cost for Deep Sub-micron Integrated Circuits

Jun Juan Du, Yuanfu Zhao, Lixin Yu

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Abstract

Enhancing test quality and restraining test cost are two main topics in the domain of test and design for testability of deep sub-micron integrated circuits. This paper presents a multi-fault oriented test and DFT resolution scheme for DSM IC. The scheme can enhance the test quality of deep sub-micron chips by using a test suite consisted of stuck-at fault test, delay fault test and delta-IDDQ test. And it can restrain the increase of test cost by adopting a special ATPG strategy to reduce scan-based stuck-at test patterns. A design paradigm of 0.18 mum MCU to which the scheme is applied is also introduced in the paper

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What this paper is about

Enhancing test quality and restraining test cost are two main topics in the domain of test and design for testability of deep sub-micron integrated circuits. This paper presents a multi-fault oriented test and DFT resolution scheme for DSM IC. The scheme can enhance the test quality of deep sub-micron chips by using a test suite consisted of stuck-at fault test, delay fault test and delta-IDDQ test. And it can restrain the increase of test cost by adopting a special ATPG strategy to reduce scan-based stuck-at test patterns. A design paradigm of 0.18 mum MCU to which the scheme is applied is also introduced in the paper

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Available abstract

Enhancing test quality and restraining test cost are two main topics in the domain of test and design for testability of deep sub-micron integrated circuits. This paper presents a multi-fault oriented test and DFT resolution scheme for DSM IC. The scheme can enhance the test quality of deep sub-micron chips by using a test suite consisted of stuck-at fault test, delay fault test and delta-IDDQ test. And it can restrain the increase of test cost by adopting a special ATPG strategy to reduce scan-based stuck-at test patterns. A design paradigm of 0.18 mum MCU to which the scheme is applied is also introduced in the paper

Key concepts: Automatic test pattern generation, Design for testing, Test compression, Fault coverage, Testability, Test suite, Test (biology), Scheme (mathematics)

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