A fast low noise CMOS charge sensitive preamplifier for column parallel CCD readout

A fast, low noise charge sensitive preamplifier for column parallel CCD readout application is presented. This prototype has been implemented on a commercial CMOS 65nm process. This preamplifier consists of a two stage transconductance amplifier with capacitive feedback to accommodate two gain ranges and a second transconductance amplifier to reset the circuit. An equivalent noise charge of 37 electrons for a 100ns readout cycle time is achieved for a power consumption of 5mW. Novel design techniques used in this circuit will be presented in detail along with measurement results obtained on the prototype.