A parallel hardware architecture of deblocking filter in H264/AVC

This paper describes an efficient hardware architecture for the deblocking filter used in H.264/AVC baseline profile video coding standard and optimized for real time implementation. Thus, the deblocking filter is a computationally and data intensive tool resulting in an increased execution time of both encoding and decoding processes. In fact, the processing order of the filter and the memory organization are rearranged to facilitate the deblocking of the pixels in a parallel fashion and to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. The proposed architecture is implemented in synthesizable HDL at RTL level and verified with the reference software. This hardware is designed to be used as part of a complete H.264/AVC decoder.