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An FPGA implementation of the floating point addition

Chokri Souani, Mariem Abid, Rached Tourki

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Abstract

Recent algorithms require a great number of arithmetic operations. Some algorithms require adequate precision imposing, the use of a long register for arithmetic operators. In this paper, the authors present a floating point format and its FPGA implementation for the addition operation. This format is different from the IEEE standard format, but is able to satisfy a sufficiently large dynamic of operators with an appropriate precision.

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What this paper is about

Recent algorithms require a great number of arithmetic operations. Some algorithms require adequate precision imposing, the use of a long register for arithmetic operators. In this paper, the authors present a floating point format and its FPGA implementation for the addition operation. This format is different from the IEEE standard format, but is able to satisfy a sufficiently large dynamic of operators with an appropriate precision.

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Available abstract

Recent algorithms require a great number of arithmetic operations. Some algorithms require adequate precision imposing, the use of a long register for arithmetic operators. In this paper, the authors present a floating point format and its FPGA implementation for the addition operation. This format is different from the IEEE standard format, but is able to satisfy a sufficiently large dynamic of operators with an appropriate precision.

Key concepts: Field-programmable gate array, Computer science, Floating point, IEEE floating point, Double-precision floating-point format, Single-precision floating-point format, Point (geometry), Arithmetic

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